1. Field of the Invention
The present invention relates to a backplane bus for interconnecting one or more microprocessors, memory modules, and input/output (I/O) peripheral boards. Specifically, the invention relates to a method and apparatus to expand the width of the data bus portion of the backplane bus without the use of additional byte select lines. According to the present invention, devices designed for previous unexpanded systems are still suitable for use in the expanded system.
2. Description of the Related Art
The processing requirements of computer systems for personal and business needs continuously become more demanding. For instance, more complex application programs for use with local area networks are continuously being developed. Moreover, many multi-user systems provide access to more than one operating environment, such as UNIX and DOS, on the same system.
In general, the computers servicing these needs are single processor systems conforming to conventional architectures using a standard input/output I/O bus such as the Extended Industry Standard Architecture (EISA). New and more powerful systems constantly emerge. However, upgrading an old system generally requires investing in substantial hardware modifications or buying a new system.
One solution to the constantly changing power of microprocessors controlling a system is the CUPID architecture designed by AST Research Inc. In the CUPID architecture, the microprocessor based central processing unit. (CPU) and the memory unit are not permanently attached to the backplane bus, but are removable circuit boards running at their own speed, asynchronous with the backplane bus operations. Thus, when more power from the microprocessor is desired, a faster CPU can replace the existing CPU.
However, as processing power demands increase, application software and operating systems would benefit from an architecture similar to the CUPID architecture, but which has multiprocessor capabilities to provide parallel processing and high interactivity and batch performance.
Some multiprocessor bus configurations have been proposed such as the Micro-Channel architecture by IBM. However, expanding the width of the interconnecting bus, once the bus size is initially selected, generally requires adding additional byte select lines on the bus to control I/O operations. This results in modifications to the interconnecting bus. The modifications to the backplane are not difficult. However, if the bus has new control lines, the circuit boards designed for the narrower bus may not function properly on the wider bus. Accordingly, to use an expanded bus often requires redesigning of the circuit boards used in connection with the bus. This again leads to substantial expense for one who wishes to upgrade a system.